01 · Design Under Test
Streams the agent loop live: plan → write → simulate → repair, closing only when checks pass AND functional coverage ≥ target.
02 · Live Run
◇
Awaiting design. Load an example or paste RTL, then run.
Functional Coverage Bins
Coverage Traceability
Run Summary
Generated SystemVerilog Testbench
Testbench (
To attach the assertions to the DUT, add the
testbench.sv) is what AVerify compiled and ran on the open-source engine. The
SVA assertions (assertions.sv) and the covergroup (guarded by
AV_COMMERCIAL_SIM) are for commercial simulators — Icarus and Verilator cannot execute them, so
AVerify does not simulate them.
How to run these files
| Icarus Verilog (free) | iverilog -g2012 -s tb_dut -o sim testbench.sv dut.sv && vvp sim |
| Verilator (free; SVA yes, covergroups no) | verilator --binary --timing --assert testbench.sv dut.sv && obj_dir/Vtb_dut |
| Synopsys VCS | vcs -sv +define+AV_COMMERCIAL_SIM testbench.sv assertions.sv dut.sv -o sim && ./sim |
| Siemens Questa | vlog -sv +define+AV_COMMERCIAL_SIM testbench.sv assertions.sv dut.sv && vsim -c tb_dut -do "run -all; quit" |
| Cadence Xcelium | xrun -sv -define AV_COMMERCIAL_SIM testbench.sv assertions.sv dut.sv |
bind line from the comment at the top of
assertions.sv. Formal (JasperGold, SymbiYosys) takes assertions.sv + dut.sv.